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ds07-12609-3e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit microcontroller cmos f 2 mc-8fx mb95160m series mb95f168m/f168n/f168j/fv100d-103 description the mb95160m series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock sub pll clock (continued)
mb95160m series 2 (continued) ? timer 8/16-bit compound timer 2 channels can be used to interval timer, pw c timer, pwm timer and input capture. 8/16-bit ppg 2 channels 16-bit ppg 1 channel time-base timer 1 channel watch prescaler 1 channel ? lin-uart 1 channel lin function, clock asynchronous (uart) or cloc k synchronous (sio) serial data transfer capable full duplex double buffer ? uart/sio 1 channel clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable full duplex double buffer ? i 2 c* 1 channel built-in wake-up function ? external interrupt 8 channels interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8 channels 8-bit or 10-bit resolution can be selected. ? lcd controller (lcdc) 32 seg 4 com (max 128 pixels) with blinking function ? low-power consumption (standby) mode stop mode sleep mode watch mode time-base timer mode ? i/o port the number of maximum ports : max 53 port configuration - general-purpose i/o ports (n-ch open drain) : 2 ports - general-purpose i/o ports (cmos) : 51 ports ? programmable input voltage levels of port automotive input level / cmos input level / hysteresis input level ? flash memory security function protects the content of flash memory * : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb95160m series 3 product lineup (continued) part number* 1 parameter mb95f168m mb95f168n MB95F168J type flash memory product rom capacity 60 kbytes ram capacity 2 kbytes reset output yes no clock system dual clock low voltage detection reset no yes clock supervisor no yes cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61. 5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) ports (max 53 ports) general-purpose i/o port (n-ch open drain) : 2 ports general-purpose i/o port (cmos) : 51 ports programmable input voltage levels of port : automotive input level / cmos input level / hysteresis input level time-base timer (1 channel) interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32. 8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz (f or dual clock product) : min 250 ms wild register capable of replacing 3 bytes of rom data i 2 c (1 channel) master/slave sending and receiving bus error function and arbitration function detecting transmitting direction function start condition repeated generat ion and detection functions built-in wake-up function uart/sio (1 channel) data transfer capable in uart/sio full duplex double buffer, variable data length (5/6/7/8-b it), built-in baud rate generator nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock synchronous (sio) or clock asynchr onous (uart) serial data transfer capable lin-uart (1 channel) dedicated reload timer allowing a wide range of communication speeds to be set. full duplex double buffer. capable of serial data transfer synchr onous or asynchronous to clock signal. lin functions available as the lin master or lin slave. 8/10-bit a/d converter (8 channels) 8-bit or 10-bit resolution can be selected. option* 2 peripheral functions
mb95160m series 4 (continued) *1 : mask rom products are currently under consideration. *2 : for details of option, refer to ? mask option?. note : part number of evaluation product in mb95160m se ries is mb95fv100d-103. w hen using it, the mcu board (mb2146-303a) is required. part number* 1 parameter mb95f168m mb95f168n MB95F168J lcd controller (lcdc) com output : 4 (max) seg output : 32 (max) lcd drive power supply (bias) pin : 4 32 seg 4 com : 128 pixels can be displayed. duty lcd mode operable in lcd standby mode with blinking function built-in division resistance for lcd drive 8/16-bit compound timer (2 channels) each channel of the timer can be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pw m function, capture function, and square wave form output count clock : 7 internal clocks and external clock can be selected. 16-bit ppg (1 channel) pwm mode or one-shot mo de can be selected. counter operating clock : eight selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ? 8-bit ppg 2 channels ? or ? 16-bit ppg 1 channel ? . counter operating clock : eight selectable clock sources watch counter count clock : four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63. (capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) watch prescaler (1 channel) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (8 channels) interrupt by edge detection (rising, falling, or both edges can be selected.) can be used to recover from standby modes. flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time: 20 years erase can be performed on each block block protection with external programming voltage flash security feature for protec ting the content of the flash standby mode sleep, stop, watch, and time-base timer peripheral functions
mb95160m series 5 oscillation stabilization wait time the initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. the maximum value is shown as follows. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 14 -2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) part number package mb95f168m/f168n/f168j mb95fv100d-103 fpt-64p-m23 fpt-64p-m24 bga-224p-m08
mb95160m series 6 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only the functions of t he mb95160m series but also those of other products to support software development for mu ltiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by the mb95160m series ar e therefore access-barred. read/write access to these access-barred addresses may cause per ipheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or written unexpectedly). also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory products, do not use these values in the program. the functions corresponding to certain bits in single- byte registers may not be supported on some flash memory products. however, reading or writing to these bits w ill not cause malfunction of the hardware. also, as the evaluation and flash memory products are designed to ha ve identical software operation, no particular precau- tions are required. ? difference of memory spaces if the amount of memory on the evaluation product is diff erent from that of the flash memory products, carefully check the difference in the amount of memory from th e model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage is different among t he evaluation and flash memory products. for details of operating voltage, refer to ? electrical characteristics?
mb95160m series 7 pin assignment (top view) (fpt-64p-m23,fpt-64p-m24) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 av cc avr p14/ppg0 p1 3 /trg0/adtg p12/uck0 p11/uo0 p10/ui0 p24/ec0/ s da0 p2 3 /to01/ s cl0 p22/to00 p21/ppg01 p20/ppg00 mod x0 x1 v ss v cc c x1a x0a r s t p90/v 3 p91/v2 p92/v1 p9 3 /v0 p94 p95 pa0/com0 pa1/com1 pa2/com2 pa 3 /com 3 pb0/ s eg00 av ss p00/int00/an00/ s eg 3 1 p01/int01/an01/ s eg 3 0 p02/int02/an02/ s eg29 p0 3 /int0 3 /an0 3 / s eg2 8 p04/int04/an04/ s eg27 p05/int05/an05/ s eg26 p06/int06/an06/ s eg25 p07/int07/an07/ s eg24 p67/ s eg2 3 / s in p66/ s eg22/ s ot p65/ s eg21/ s ck p64/ s eg20/ec1 p6 3 / s eg19/to11 p62/ s eg1 8 /to10 p61/ s eg17/ppg11 p60/ s eg16/ppg10 pc7/ s eg15 pc6/ s eg14 pc5/ s eg1 3 pc4/ s eg12 pc 3 / s eg11 pc2/ s eg10 pc1/ s eg09 pc0/ s eg0 8 pb7/ s eg07 pb6/ s eg06 pb5/ s eg05 pb4/ s eg04 pb 3 / s eg0 3 pb2/ s eg02 pb1/ s eg01 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 lqfp-64
mb95160m series 8 pin description (continued) pin no. pin name i/o circuit type* function 1av cc ? a/d converter power supply pin 2 avr ? a/d converter reference input pin 3 p14/ppg0 h general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 output. 4 p13/trg0/ adtg general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 trigger input (trg0) and a/d converter trigger input (adtg) . 5 p12/uck0 general-purpose i/o port. the pin is shared with uart/sio ch.0 clock i/o. 6 p11/uo0 general-purpose i/o port. the pin is shared with uart/sio ch.0 data output. 7 p10/ui0 g general-purpose i/o port. the pin is shared with uart/sio ch.0 data input. 8 p24/ec0/ sda0 i general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.0 clock input (ec0) and i 2 c ch.0 data i/o (sda0) . 9 p23/to01/ scl0 general-purpose i/o port. the pin is shared with 8/16-bit co mpound timer ch.0 output (to01) and i 2 c ch.0 clock i/o (scl0) . 10 p22/to00 h general-purpose i/o port. the pin is shared with 8/16-b it compound timer ch.0 output. 11 p21/ppg01 general-purpose i/o port. the pin is shared with 8/16-bit ppg ch.0 output. 12 p20/ppg00 general-purpose i/o port. the pin is shared with 8/16-bit ppg ch.0 output. 13 mod b operating mode designation pin 14 x0 a main clock oscillation pin 15 x1 16 v ss ? power supply pin (gnd) 17 v cc ? power supply pin 18 c ? capacitor connection pin 19 x1a a sub clock oscillation pins (32 khz) 20 x0a 21 rst b? reset pin 22 p90/v3 r general-purpose i/o port. the pins are shared with power supply pin for lcdc drive. 23 p91/v2 24 p92/v1 25 p93/v0
mb95160m series 9 (continued) pin no. pin name i/o circuit type* function 26 p94 s general-purpose i/o port. 27 p95 28 pa0/com0 m general-purpose i/o port. the pins are shared with lc dc com output (com0 to com3). 29 pa1/com1 30 pa2/com2 31 pa3/com3 32 pb0/seg00 m general-purpose i/o port. the pins are shared with lcdc seg output (seg00 to seg07). 33 pb1/seg01 34 pb2/seg02 35 pb3/seg03 36 pb4/seg04 37 pb5/seg05 38 pb6/seg06 39 pb7/seg07 40 pc0/seg08 m general-purpose i/o port. the pins are shared with lcdc seg output (seg08 to seg15). 41 pc1/seg09 42 pc2/seg10 43 pc3/seg11 44 pc4/seg12 45 pc5/seg13 46 pc6/seg14 47 pc7/seg15 48 p60/seg16/ ppg10 m general-purpose i/o port. the pins are shared with lcdc seg output (seg16, seg17) and 8/16-bit ppg ch.1 output (ppg10, ppg11) . 49 p61/seg17/ ppg11 50 p62/seg18/ to10 general-purpose i/o port. the pin is shared with lcdc seg output (seg18) and 8/16-bit compound timer ch.1 output (to10) .
mb95160m series 10 (continued) * : refer to ? i/o circuit type? for details on the i/o circuit types. pin no. pin name i/o circuit type* function 51 p63/seg19/ to11 m general-purpose i/o port. the pin is shared with lcdc se g output (seg19) and 8/16-bit compound timer ch.1 output (to11) . 52 p64/seg20/ ec1 general-purpose i/o port. the pin is shared with lcdc se g output (seg20) and 8/16-bit compound timer ch.1 clock input (ec1) . 53 p65/seg21/ sck general-purpose i/o port. the pin is shared with lcdc se g output (seg21) and lin-uart clock i/o (sck) . 54 p66/seg22/ sot general-purpose i/o port. the pin is shared with lcdc se g output (seg22) and lin-uart data output (sot) . 55 p67/seg23/ sin n general-purpose i/o port. the pin is shared with lcdc se g output (seg23) and lin-uart data input (sin) . 56 p07/int07/ an07/seg24 f general-purpose i/o port. the pins are shared with external interrupt input (int00 to int07) , a/d analog input (an00 to an07 ) and lcdc seg output (seg24 to seg31) . 57 p06/int06/ an06/seg25 58 p05/int05/ an05/seg26 59 p04/int04/ an04/seg27 60 p03/int03/ an03/seg28 61 p02/int02/ an02/seg29 62 p01/int01/ an01/seg30 63 p00/int00/ an00/seg31 64 av ss ? power supply pin (gnd) of a/d converter
mb95160m series 11 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance : approx. 1 m ? low-speed side feedback resistance : approx. 10 m ? b only for input hysteresis input b? hysteresis input reset output fcmos output lcd output hysteresis input analog input automotive input gcmos output cmos input hysteresis input with pull-up control automotive input x0 (x0a) n-ch x1 (x1a) standby control clock input mode input n-ch reset input reset output p-ch n-ch standby control external interrupt control digital output digital output hysteresis input lcd control analog input lcd output a/d control automotive input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input automotive input
mb95160m series 12 (continued) type circuit remarks h cmos output hysteresis input with pull-up control automotive input i n-ch open drain output cmos input hysteresis input automotive input m cmos output lcd output hysteresis input automotive input n cmos output lcd output cmos input hysteresis input automotive input p-ch p-ch n-ch r pull-up control standby control digital output digital output hysteresis inpu t automotive inpu t n-ch standby control hysteresis input cmos input automotive input digital output p-ch n-ch standby control digital output digital output hysteresis input lcd control lcd output automotive input p-ch n-ch standby control digital output digital output hysteresis input lcd control lcd output cmos input automotive input
mb95160m series 13 (continued) type circuit remarks r cmos output lcd power supply hysteresis input automotive input s cmos output lcd power supply hysteresis input automotive input p-ch n-ch standby control lcd control digital output digital output hysteresis input lcd built-in internal split resistor i/o automotive input p-ch n-ch standby control digital output digital output hysteresis input automotive input
mb95160m series 14 handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the vcc power-supply voltage. for stabilization, in principle, keep the variation in vcc ripple (p-p value) in a commercial frequency range (50/60 hz) not to exceed 10% of the standard vcc valu e and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mome ntary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from sub clock mode or stop mode. pin connection ? treatment of unused pin leaving unused input pins unconnected can cause abnorma l operation or latch-up, leaving to permanent dam- age. unused input pins should al ways be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device.
mb95160m series 15 ? mode pin (mod) connect the mod pin directly to v cc or v ss . to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mod pin to v cc or v ss and to provide a low-impedance connection. use a ceramic capacitor or a capacitor with equivalent frequency characteristics. a bypass capacitor of v cc pin must have a capacitance value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. ? analog power supply always set the same potential to av cc and v cc pins. when v cc > av cc , the current may flow through the an00 to an07 pins. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = avr = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. c c s c pin connection diagram
mb95160m series 16 programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information on applicable adapter models and parallel programmers, contact the following: flash support group, inc. tel: + 81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to addresses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to 17222. 2) load program data to pr ogrammer addresses 11000 h to 1ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-64p-m23 tef110-95f168hpmc af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-64p-m24 tef110-95f168hpmc1 *: programmer addresses are corresponding to cpu a ddresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the par allel programmer to program or erase data in flash memory. flash memory cpu address programmer address* 60 kbytes 1000 h 11000 h ffff h 1ffff h
mb95160m series 17 block diagram p14/ppg0 av ss avr av cc p21/ppg01 p22/to00 p23/to01/scl0 p24/ec0/sda0 (p00/an00 to p07/an07) p12/uck0 p62/seg18/to10 p63/seg19/to11 p00/int00 to p07/int07 p10/ui0 p64/seg20/ec1 rst x0/x1 x0a/x1a mod, v ss , v cc , c p13/trg0/adtg p20/ppg00 p11/uo0 uart/sio rom ram f 2 mc-8fx cpu p61/seg17/ppg11 p60/seg16/ppg10 p65/seg21/sck p66/seg22/sot p67/seg23/sin p90/v3 to p93/v0 p94/p95 pa0/com0 to pa3/com3 pb0/seg00 to pb7/seg07 pc0/seg08 to pc7/seg15 (p00/seg31 to p07/seg24) i 2 c lcdc lin-uart reset control clock control watch prescaler watch counter external interrupt 16-bit ppg 8/16-bit ppg ch.0 8/16-bit compound timer ch.0 8/10-bit a/d converter port port interrupt control wild register 8/16-bit ppg ch.1 8/16-bit compound timer ch.1 other pins internal bus
mb95160m series 18 cpu core 1. memory space memory space of the mb95160m series is 64 kbytes and consists of i/o area, data area, and program area. the memory space includes special-purpose areas such as the general-purpose registers and vector table. memory map of the mb95160m series is shown below. memory map 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h exterded i/o mb95fv100d-10 3 i/o 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h exterded i/o mb95f16 8 m mb95f16 8 n mb95f16 8 j i/o 0 88 0 h regi s ter regi s ter acce ss prohi b ited fl as h memory 60k b yte s fl as h memory 60k b yte s ram 2k b yte s ram 3 .75k b yte s
mb95160m series 19 2. register the mb95160m series has two types of registers; dedica ted registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for us e as a condition code register (ccr). (refer to the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower 1 byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower 1 byte is used. index register (ix) : a 16-bit re gister for index modification. extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit regi ster to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register. pc al tl ah th ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dp2 dp1 dp0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95160m series 20 the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic operat ion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is set to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by these bits. il1 il0 interrupt level priority 00 0 high low (no interruption) 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower
mb95160m series 21 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-register. up to a total of 32 banks can be used on t he mb95160m series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 this address = 0100 h + 8 (rp) r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1f8 h 1ff h bank 31 bank 0 8-bit register bank configuration 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance.
mb95160m series 22 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010 x 011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset factor register r/w xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (disabled) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h to 0015 h ? (disabled) ?? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 001b h ? (disabled) ?? 001c h pdr9 port 9 data register r/w 00000000 b 001d h ddr9 port 9 direction register r/w 00000000 b 001e h pdra port a data register r/w 00000000 b 001f h ddra port a direction register r/w 00000000 b 0020 h pdrb port b data register r/w 00000000 b 0021 h ddrb port b direction register r/w 00000000 b 0022 h pdrc port c data register r/w 00000000 b 0023 h ddrc port c direction register r/w 00000000 b 0024 h to 002c h ? (disabled) ??
mb95160m series 23 (continued) address register abbreviation register name r/w initial value 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h to 0035 h ? (disabled) ?? 0036 h t01cr1 8/16-bit compound timer 01 contro l status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 contro l status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 contro l status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 contro l status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h to 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg status control re gister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg status control re gister (lower byte) ch.0 r/w 00000000 b 0044 h to 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit control register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6/ch.7 r/w 00000000 b 004c h to 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h smc10 uart/sio serial mode cont rol register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode cont rol register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b
mb95160m series 24 (continued) address register abbreviation register name r/w initial value 0059 h tdr0 uart/sio serial output da ta register ch. 0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 005f h ? (disabled) ?? 0060 h ibcr00 i 2 c bus control register 0 ch.0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch.0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch.0 r 00000000 b 0063 h iddr0 i 2 c data register ch.0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch.0 r/w 00000000 b 0065 h iccr0 i 2 c clock control register ch.0 r/w 00000000 b 0066 h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d conv erter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000 x 0000 b 0073 h swre0 flash memory sector writing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? register bank pointer (rp) , mirror of direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b
mb95160m series 25 (continued) address register abbreviation register name r/w initial value 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting re gister (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/ 01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/ 11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h to 0fa9 h ? (disabled) ??
mb95160m series 26 (continued) address register abbreviation register name r/w initial value 0faa h pdcrh0 16-bit ppg down counter register (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter register (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer register (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer register (lower byte) ch.0 r/w 11111111 b 0fb0 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate ge nerator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate ge nerator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler selecting register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate gene rator setting register ch.0 r/w 00000000 b 0fc0 h to 0fc2 h ? (disabled) ?? 0fc3 h aidrl a/d input disable regi ster (lower byte) r/w 00000000 b 0fc4 h lcdcc lcdc control register r/w 00010000 b 0fc5 h lcdce1 lcdc enable register 1 r/w 00110000 b 0fc6 h lcdce2 lcdc enable register 2 r/w 00000000 b 0fc7 h lcdce3 lcdc enable register 3 r/w 00000000 b 0fc8 h lcdce4 lcdc enable register 4 r/w 00000000 b 0fc9 h lcdce5 lcdc enable register 5 r/w 00000000 b 0fca h ? (disabled) ?? 0fcb h lcdcb1 lcdc blinking setting register 1 r/w 00000000 b 0fcc h lcdcb2 lcdc blinking setting register 2 r/w 00000000 b 0fcd h to 0fdc h lcdram lcdc display ram r/w 00000000 b 0fdd h to 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b
mb95160m series 27 (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (disabled) ?. re ading the ? (disabled) ? returns an undefined value. address register abbreviation register name r/w initial value 0fe4 h to 0fe6 h ? (disabled) ?? 0fe7 h ilsr2 input level select register 2 r/w 00000000 b 0fe8 h , 0fe9 h ? (disabled) ?? 0fea h csvcr clock supervisor control register r/w 00011100 b 0feb h to 0fed h ? (disabled) ?? 0fee h ilsr input level selecting register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95160m series 28 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] (unused) irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch.0 irq16 ffda h ffdb h l16 [1 : 0] (unused) irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] time-base timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] (unused) irq21 ffd0 h ffd1 h l21 [1 : 0] 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95160m series 29 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc , av cc vss ? 0.3 vss + 6.0 v *2 avr vss ? 0.3 vss + 6.0 *2 power supply voltage for lcd v0 to v3 vss ? 0.3 vss + 6.0 v *3 input voltage* 1 v i vss ? 0.3 vss + 6.0 v *4 output voltage* 1 v o vss ? 0.3 vss + 6.0 v *4 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 5 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 5 ?l? level maximum output current i ol ? 15 ma applicable to pins* 5 ?l? level average current i olav ? 4ma applicable to pins* 5 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh ? ? 15 ma applicable to pins* 5 ?h? level average current i ohav ? ? 4ma applicable to pins* 5 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins) power consumption pd ? 320 mw operating temperature t a ? 10 + 85 c storage temperature tstg ? 55 + 150 c
mb95160m series 30 (continued) *1 : the parameter is based on v ss = 0.0 v. *2 : apply equal potential to av cc and v cc . avr should not exceed av cc + 0.3 v. *3 : v0 to v3 should not exceed v cc + 0.3 v. *4 : v i and vo should not exceed v cc + 0.3 v. v i must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some m eans with external components, the i clamp rating supersedes the v i rating. *5 : applicable to pins : p00 to p07, p10 to p14, p20 to p22,p60 to p67, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7 ? use within recommended operating conditions. ? use at dc voltage (current). ? + b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this affects other devices. ? note that if the + b signal is inputted when the mi crocontroller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than t he a/d input pins (lcd drive pins, etc.) cannot accept + b signal input. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95160m series 31 2. recommended operating conditions (vss = 0.0 v) *1 : the values vary with the operating fr equency, machine clock or analog guarantee range. *2 : the value is 2.88 v when the low voltage detection rese t is used. the device operates normally during the time between 2.88 v and low voltag e detection, and between re lease voltage and 2.88 v. (continued) parameter symbol condi- tions value unit remarks min max power supply voltage v cc , av cc ? 2.42* 1, * 2 5.5* 1 v in normal operating other than mb95fv100d- 103 2.3 5.5 hold condition in stop mode 2.7 5.5 in normal operating mb95fv100d- 103 2.3 5.5 hold condition in stop mode power supply voltage for lcd v0 to v3 v ss v cc v the range of liquid crystal power supply: without up-conversion (the optimal value depends on liquid crystal display elements used.) a/d converter reference input voltage avr 4.0 av cc v smoothing capacitor c s 0.1 1.0 f*3 operating temperature t a ? 10 + 85 c other than mb95fv100d-103 + 5 + 35 c mb95fv100d-103
mb95160m series 32 (continued) *3 : use a ceramic capacitor or a capacitor with equiva lent frequency characteristic s. a bypass capacitor of v cc pin must have a capacitor value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. c c s c pin connection diagram
mb95160m series 33 3. dc characteristics (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level input voltage v ih1 p10, p67 *1 0.7 v cc ? v cc + 0.3 v when selecting cmos input level v ih2 p23, p24 *1 0.7 v cc ? v ss + 5.5 v v iha p00 to p07, p10 to p14, p20 to p22, p60 to p67, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7 ? 0.8 v cc ? v cc + 0.3 v port inputs if auto- motive input levels are selected v ihs1 p00 to p07, p10 to p14, p20 to p22, p60 to p67, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7 *1 0.8 v cc ? v cc + 0.3 v hysteresis input v ihs2 p23, p24 *1 0.8 v cc ? v ss + 5.5 v v ihm rst , mod ? 0.7 v cc ? v cc + 0.3 v cmos input ?l? level input voltage v il p10,p23, p24,p67 *1 v ss ? 0.3 ? 0.3 v cc v hysteresis input (when selecting cmos input level) v ila p00 to p07, p10 to p14, p20 to p24, p60 to p67, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7 ? v ss ? 0.3 ? 0.5 v cc v port inputs if automotive input levels are selected v ils p00 to p07, p10 to p14, p20 to p24, p60 to p67, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm rst , mod ? v ss ? 0.3 ? 0.3 v cc v hysteresis input ?h? level output voltage v oh output pins other than p00 to p07 i oh = ? 4.0 ma v cc ? 0.5 ?? v
mb95160m series 34 (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?l? level output voltage v ol output pins other than p00 to p07, rst * 2 i ol = 4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li ports other than p23, p24 0.0 v < v i < v cc ? 5 ? + 5 a when the pull-up prohibition setting pull-up resistor r pull p10 to p14, p20 to p22 v i = 0.0 v 25 50 100 k ? when the pull-up permission setting input capacitance c in other than av cc , av ss , avr, v cc , v ss f = 1 mhz ? 515pf power supply current* 3 i cc v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 9.5 12.5 ma at other than flash memory writing and erasing ? 30.0 35.0 ma at flash memory writing and erasing f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 15.2 20.0 ma at other than flash memory writing and erasing ? 35.7 42.5 ma at flash memory writing and erasing i ccs f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 7.5 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 12.0 ma i ccl f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) t a = + 25 c ? 45 100 a i ccls f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) t a = + 25 c ? 10 81 a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ? 4.6 27.0 a
mb95160m series 35 (continued) (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : the value is 2.88 v when the low voltage detection reset is used. *2 : product without clock supervisor only *3 : ? the power-supply current is determined by the exter nal clock. when both low voltage detection option and clock supervisor option are selected, the powe r-supply current will be a value of adding current consumption of the low vo ltage detection circuit (i lv d ) and current consumption of built-in cr oscillator (i csv ) to the specified value. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i ccmpll v cc (external clock operation) f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 9.3 12.5 ma f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 14.9 20.0 ma i ccspll f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 160 400 a i cts f ch = 10 mhz time-base timer mode t a = + 25 c ? 0.15 1.10 ma i cch sub stop mode t a = + 25 c ? 520 a i a av cc f ch = 16 mhz at operating of a/d conversion ? 2.4 4.7 ma i ah f ch = 16 mhz at stopping of a/d conversion t a = + 25 c ? 15 a lcd internal division resistance r lcd ? between v3 and v ss ? 300 ? k ? com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 5.0 v ?? 5k ? seg00 to seg31 output impedance r vseg seg00 to seg31 ?? 7k ? lcd leak current i lcdl v0 to v3, com0 to com3 seg00 to seg31 ? ? 1 ? + 1 a
mb95160m series 36 4. ac characteristics (1) clock timing (vcc = 2.42 v to 5.5 v, vss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name conditions value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 3.00 ? 4.06 mhz main pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll clock cycle time t hcyl x0, x1 61.5 ? 1000 ns when using oscillation circuit 30.8 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub clock input clock pulse width t wh1 t wl1 x0 61.5 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95160m series 37 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 ? input wave form for using external clock (main clock) x0 x1 f ch x0 f ch x1 c1 c2 microcontroller microcontroller ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.2 v cc x0a 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl2 ? input wave form for using external clock (sub clock) x0a x1a f cl x0a f cl x1a c1 c2 microcontroller microcontroller ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open
mb95160m series 38 (2) source clock/machine clock (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock di vision ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machine clock divisi on ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the s ource clock can be selected as follows. ? main clock divided by 2 ? pll multiplication of main clock (selec t from 1, 2, 2.5, 4 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol condi- tions value unit remarks min typ max source clock cycle time* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 8.125 mhz, pll multiplied by 2 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp 0.50 ? 16.25 mhz when using main clock f spl 16.384 ? 131.072 khz when using sub clock machine clock cycle time* 2 (minimum instruction execution time) t mclk 61.5 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock
mb95160m series 39 f ch (main oscillation) f cl (sub oscillation) divided by 2 main pll 1 2 2.5 divided by 2 sub pll 2 3 4 sclk ( source clock ) mclk ( machine clock ) clock mode select bit ( sycc : scs1, scs0 ) division circuit 1 1/4 1/8 1/16 4 ? outline of clock generation block
mb95160m series 40 ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95f168m/f168n/f168j ? operating voltage - operating frequency (when t a = + 5 c to + 35 c) ? mb95fv100d-103 2.42 5.5 16.25 mhz 0.5 mhz 5.5 2.42 3 mhz 10 mhz 3 .5 1 3 1.072 khz 16. 38 4 khz 3 2 khz source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operati on guarantee range main clock mode and main pll mode operation guarantee range 10 mhz 0.5mhz 2.7 3 mhz 5.5 131.072 khz 16.384 khz 2.7 32 khz 5.5 3.5 16.25 mhz source clock frequency (f sp ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operati on guarantee range main clock mode and main pll mode operation guarantee range
mb95160m series 41 [mhz] 16.25 16 15 12 10 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8 .125 10 [mhz] ? main pll operation frequency main clock frequency ( f mp ) source clock frequency (f sp ) 2.5 2 1 4
mb95160m series 42 (3) external reset (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation time of oscillator is th e time that the amplitude r eaches 90%. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillators, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter sym- bol pin name condi- tions value unit remarks min max rst ?l? level pulse width t rstl rst ? 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 100 ? s at stop mode, sub clock mode, sub sleep mode, and watch mode 100 ? s at time-base timer mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 100 s rst x0 ? at normal operating ? at stop mode, sub clock mode, su b sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95160m series 43 (4) power-on reset (vss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, set the slope of rising with in 30 mv/ms as shown below. parameter symbol pin name conditions value unit remarks min max power supply rising time t r v cc ? ? 50 ms power supply cutoff time t off 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode limiting the slope of rising within 30 mv/ms is recommended.
mb95160m series 44 (5) peripheral input timing (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, trg0/adtg ? 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih int00 to int07, ec0, ec1, trg0/adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95160m series 45 (6) uart/sio, serial i/o timing (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v uck0 uo0 ui0 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v uck0 uo0 ui0 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95160m series 46 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recepti on data is performed at risi ng edge or falling edge of the serial clock. *2 : serial clock delay function is used to del ay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95160m series 47 0. 8 v 0. 8 v 2.4 v t s lovi t iv s hi t s hixi 2.4 v 0. 8 v s ck s ot s in t s cyc 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc t slove t ivshe t shixe 2.4 v 0.8 v t r t f sck sot sin t slsh t shsl 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95160m series 48 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95160m series 49 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc t shove t ivsle t slixe 2.4 v 0.8 v t f t r sck sot sin t shsl t slsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc internal shift clock mode external shift clock mode
mb95160m series 50 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 0. 8 v 0. 8 v t s hovi 2.4 v 0. 8 v 2.4 v 0. 8 v t s cyc t s ovli t iv s li t s lixi 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc
mb95160m series 51 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 2.4 v 0. 8 v t s lovi 2.4 v 0. 8 v 2.4 v 0. 8 v t s cyc t s ovhi t iv s hi t s hixi 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc
mb95160m series 52 (8) i 2 c timing (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the devi ce dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. *4 : refer to ? ? note of sda and scl set-up time?. note : the rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input data set-up time cannot be satisfied. parameter symbol pin name conditions value unit standard-mode fast-mode min max min max scl clock frequency f scl scl0 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl0 sda0 4.0 ? 0.6 ? s scl clock ?l? width t low scl0 4.7 ? 1.3 ? s scl clock ?h? width t high scl0 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl0 sda0 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl0 sda0 0 3.45* 2 00.9* 3 s data setup time sda scl t su;dat scl0 sda0 0.25* 4 ? 0.1* 4 ? s stop condition setup time scl sda t su;sto scl0 sda0 4.0 ? 0.6 ? s bus free time between stop condition and start condition t buf scl0 sda0 4.7 ? 1.3 ? s sda0 scl0 6 tcp ? note of sda and scl set-up time input data set-up time
mb95160m series 53 sda0 scl0 t wakeup t hd;sta t su;dat t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95160m series 54 (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condi- tions value* 2 unit remarks min max scl clock ?l? width t low scl0 r = 1.7 k ? , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0 (nm / 2) t mclk ? 20 (nm / 2 ) t mclk + 20 ns master mode start condition hold time t hd;sta scl0 sda0 ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl0 sda0 (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl0 sda0 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl0 sda0 ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0 (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl0 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception
mb95160m series 55 (continued) (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : ? refer to ? (2) source clock/machine clock? for t mclk . ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of i 2 c clock control register (iccr) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of i 2 c clock control register (iccr) . ? actual timing of i 2 c is determined by m and n values set by the machine clock (t mclk ) and cs4 to cs0 of iccr0 register. ? standard-mode : m and n can be set at t he range : 0.9 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode : m and n can be set at t he range : 3.3 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condi- tions value* 2 unit remarks min max stop condition detection t su;sto scl0 sda0 r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl0 sda0 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0 sda0 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0 sda0 t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl0 sda0 0 ? ns at reception data setup time t su;dat scl0 sda0 t mclk ? 20 ? ns at reception sda scl (at wakeup function) t wake- up scl0 sda0 oscillation stabilization wait time + 2 t mclk ? 20 ? ns
mb95160m series 56 (9) low voltage detection (vss = 0.0 v, t a = ? 10 c to + 85 c) parameter sym- bol condi- tions value unit remarks min typ max release voltage v dl+ ? 2.52 2.70 2.88 v at power-supply rise detection voltage v dl- 2.42 2.60 2.78 v at power-supply fall hysteresis width v hys 70 100 ? mv power-supply start voltage v off ?? 2.3 v power-supply end voltage v on 4.9 ?? v power-supply voltage change time (at power supply rise) t r 0.3 ?? s slope of power supply that reset release signal generates ? 3000 ? s slope of power supply that reset release signal generates within rating (v dl+ ) power-supply voltage change time (at power supply fall) t f 300 ?? s slope of power supply that reset detection signal generates ? 300 ? s slope of power supply that reset detection signal generates within rating (v dl- ) reset release delay time t d1 ?? 400 s reset detection delay time t d2 ?? 30 s current consumption i lvd ? 38 50 a current consumption of low voltage detection circuit only v hy s t d2 t d1 t r t f v on v cc v off v dl+ v cc v dl- internal reset signal time time
mb95160m series 57 (10) clock supervisor clock (vcc = 5.0 v 10 % , vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol condi- tions value unit remarks min typ max oscillation frequency f out ? 50 100 200 khz oscillation start time t wk ?? 10 s current consumption i csv ? 20 36 a current consumption of built-in cr oscillator, at 100 khz oscillation
mb95160m series 58 5. a/d converter (1) a/d converter electrical characteristics (av cc = v cc = 4.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol condi- tions value unit remarks min typ max resolution ? ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v full-scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v avcc 5.5 v 1.8 ? 16500 s4.0 v avcc < 4.5 v sampling time ? 0.6 ?? s 4.5 v avcc 5.5 v, at external impedance < 5.4 k ? 1.2 ?? s 4.0 v avcc < 4.5 v, at external impedance < 2.4 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain av ss ? avr v reference voltage ? av ss + 4.0 ? av cc v avr pin reference voltage supply current i r ? 600 900 a avr pin, during a/d operation i rh ?? 5 a avr pin, at stop mode
mb95160m series 59 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the ex ternal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample an d hold capacitor is insufficient, adversely affecting a/ d conversion precision. therefore, to satisfy the a/d conversion precisi on standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |v cc ? v ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit rc 4.5 v v cc 5.5 v 2.0 k ? (max) 16 pf (max) 4.0 v v cc < 4.5 v 8.2 k ? (max) 16 pf (max) comparator during sampling : on 0 2 46 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 v cc 4.5 v v cc 4.0 v 01234 0 2 4 6 8 10 12 14 16 18 20 v cc 4.5 v v cc 4.0 v (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time
mb95160m series 60 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot v ss v cc v ss v nt v cc {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = v cc ? vss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) h to n h =
mb95160m series 61 (continued) v ss v cc v ss v cc v ss v cc v nt v ss v cc 001 h 002 h 00 3 h 004 h 3 fc h 3 fd h 3 fe h 3 ff h 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h (n - 2) h (n - 1) h n h (n + 1) h { 1 l s b n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n v (n + 1) t ? v nt 1 lsb linearity error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) h to n h v ot (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 1.5 lsb [v] ideal characteristics = =
mb95160m series 62 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 5.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 4.5 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter condi- tions value unit remarks min typ max chip erase time ? ? 1* 1 15* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600 s excludes system-level overhead. erase/program cycle 10000 ?? cycle power supply voltage at erase/program 4.5 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = + 85 c
mb95160m series 63 example characteristics ? power supply current temperature (continued) i cc ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode, at external clock operating i cc ? t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main clock mode, at external clock operating i ccs ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode, at ex ternal clock operating i ccs ? t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main sleep mode, at external clock operating i ccmpll ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (main pll multiplied by 2.5) main pll mode, at external clock operating i ccmpll ? t a v cc = 5.5 v, f mp = 10, 16 mhz (main pll multiplied by 2.5) main pll mode, at external clock operating 20 15 10 5 0 2 3 4567 f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc [ma] v cc [v] 20 15 10 5 0 -50 0 +50 +100 +150 f mp = 16 mhz f mp = 10 mhz i cc [ma] t a [ c ] 20 15 10 5 0 2 3 4567 f mp =16 mhz f mp =10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz v cc [v] i cc s [ma] 20 15 10 5 0 -50 0 +50 +100 +150 f mp = 16 mhz f mp = 10 mhz t a [ c ] i cc s [ma] 2 3 4567 20 15 10 5 0 f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz v cc [v] i ccmpll [ma] 20 15 10 5 0 -50 0 +50 +100 +150 f mp = 16 mhz f mp = 10 mhz t a [ c ] i ccmpll [ma]
mb95160m series 64 (continued) i ccl ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) sub clock mode, at external clock operating i ccl ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) sub clock mode, at external clock operating i ccls ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) sub sleep mode, at external clock operating i ccls ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) sub sleep mode, at external clock operating i cct ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) clock mode, at external clock operating i cct ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) clock mode, at external clock operating 0 25 50 75 100 2 3 4567 v cc [v] i ccl [ a] 0 25 50 75 100 ? 50 0 +50 +100 +150 t a [ c ] i ccl [ a] 0 25 50 75 100 2 3 4567 v cc [v] i ccl s [ a] 0 25 50 75 100 ? 50 0 +50 +100 +150 t a [ c ] i ccl s [ a] 0 25 50 75 100 2 3 4567 v cc [v] i cct [ a] 0 25 50 75 100 ? 50 0 +50 +100 +150 t a [ c ] i cct [ a]
mb95160m series 65 (continued) i ccspll ? v cc t a = + 25 c, f mpl = 128 khz (main pll multiplied by 4) sub pll mode, at exte rnal clock operating i ccspll ? t a v cc = 5.5 v, f mpl = 128 khz (main pll multiplied by 4) sub pll mode, at external clock operating i cts ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode, at external clock operating i cts ? t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) time-base timer mode, at external clock operating i cch ? v cc t a = + 25 c, f mpl = (stop) sub stop mode, at external clock stopping i cch ? t a v cc = 5.5 v, f mpl = (stop) sub stop mode, at external clock stopping 0 25 50 75 100 125 150 175 200 2 3 4567 v cc [v] i cc s pll [ a] 0 25 50 75 100 125 150 175 200 ? 50 0 +50 +100 +150 t a [ c] i cc s pll [ a] 0.0 0.5 1.0 1.5 2.0 2 3 4567 v cc [v] i ct s [ma] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0.0 0.5 1.0 1.5 2.0 ? 50 0 +50 +100 +150 t a [ c] i ct s [ma] f mp = 16 mhz f mp = 10 mhz 0 5 10 15 20 2 3 4567 v cc [v] i cch [ a] 0 5 10 15 20 ? 50 0 +50 +100 +150 t a [ c] i cch [ a]
mb95160m series 66 (continued) i a ? av cc t a = + 25 c, f mp = 16 mhz (divided by 2) main clock mode, at external clock operating i a ? t a v cc = 5.5 v, f mp = 16 mhz (divided by 2) main clock mode, at external clock operating i r ? av cc t a = + 25 c, f mp = 16 mhz (divided by 2) main clock mode, at external clock operating i r ? t a v cc = 5.5 v, f mp = 16 mhz (divided by 2) main clock mode, at external clock operating 0 1 2 3 4 234567 av cc [v] i a [ma] 0 1 2 3 4 ? 50 0 +50 +100 +150 t a [ c ] i a [ma] 0 1 2 3 4 234567 av cc [v] i r [ma] 0 1 2 3 4 ? 50 0 +50 +100 +150 t a [ c ] i r [ma]
mb95160m series 67 ? input voltage v ih1 ? v cc and v il ? v cc t a = + 25 c v ihs1 ? v cc and v ils ? v cc t a = + 25 c v ih2 ? v cc and v il ? v cc t a = + 25 c v ihs2 ? v cc and v ils ? v cc t a = + 25 c v iha ? v cc and v ila ? v cc t a = + 25 c v ihm ? v cc and v ilm ? v cc t a = + 25 c 0 1 2 3 4 5 234567 v cc [v] v ih1 / v il [v] v ih1 v il 0 1 2 3 4 5 234567 v cc [v] v ihs1 / v ils [v] v ihs1 v ils 0 1 2 3 4 5 234567 v cc [v] v ih2 / v il [v] v ih2 v il 0 1 2 3 4 5 234567 v ihs2 / v ils [v] v ihs2 v ils v cc [v] 0 1 2 3 4 5 234567 v cc [v] v iha / v ila [v] v iha v ila 0 1 2 3 4 5 234567 v cc [v] v ihm / v ilm [v] v ihm v ilm
mb95160m series 68 ? output voltage ? pull-up v oh1 ? i oh t a = + 25 c v ol1 ? i ol t a = + 25 c v ol2 ? i ol t a = + 25 c 0.0 0.2 0.4 0.6 0. 8 1.0 -10 - 8 -6 -4 -2 0 i oh [ma] v cc - v oh1 [v] 3 v 3 . 3 v 3 .5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 4 v 2.7 v 2.5 v v cc = 2.45 v 0.0 0.2 0.4 0.6 0. 8 1.0 0246 8 10 i ol [ma] v ol1 [v] v cc = 4.0 v 3 v v cc = 3 .5 v v cc = 3 . 3 v 2.7 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 2.5 v v cc = 2.45 v 0.0 0.2 0.4 0.6 0. 8 1.0 0.0 2.0 4.0 6.0 8 .0 10.0 i ol [ma] v ol2 [v] v cc = 2.7 v v cc = 3 .0 v v cc = 2.5 v v cc = 3 . 3 v v cc = 3 .5 v v cc = 4.0 v v cc = 5.0 v v cc = 2.5 v 2.45 v r pull ? v cc t a = + 25 c 0 50 100 150 200 250 23456 v cc [v] r pull [k ? ]
mb95160m series 69 mask option * : refer to table below about clock mode select, low volta ge detection reset, clock supervisor select and reset output. no. part number mb95f168m/f168n/f168j mb95fv100d-103 specifying procedure setting disabled setting disabled 1 clock mode select* ? single-system clock mode ? dual-system clock mode dual-system clock mode changing by the switch on mcu board 2 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset specified by part number changi ng by the switch on mcu board 3 clock supervisor* ? with clock supervisor ? without clock supervisor specified by part number changi ng by the switch on mcu board 4 reset output* ? with reset output ? without reset output specified by part number mcu board switch sets as follows; ? with clock supervisor: without reset output ? without clock supervisor: with reset output 5 oscillation stabilization wait time fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch part number clock mode select low voltage detection reset clock supervisor reset output mb95f168m dual-system no no yes mb95f168n yes no yes MB95F168J yes yes no mb95fv100d-103 single-system no no yes yes no yes yes yes no dual-system no no yes yes no yes yes yes no
mb95160m series 70 ordering information part number package mb95f168mpmc mb95f168npmc MB95F168Jpmc 64-pin plastic lqfp (fpt-64p-m23) mb95f168mpmc1 mb95f168npmc1 MB95F168Jpmc1 64-pin plastic lqfp (fpt-64p-m024) mb2146-303a (mb95fv100d-103pbt) mcu board ( ) 224-pin plastic pfbga (bga-224p-m08)
mb95160m series 71 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lfqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 fujit s u limited f640 3 4 s -c-1-1 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00 0.10(.472 .004) s q 14.00 0.20(.551 .00 8 ) s q index 0. 3 2 0.05 (.01 3 .002) m 0.1 3 (.005) 0.145 0.055 (.0057 .0022) "a" .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.50 0.20 (.020 .00 8 ) 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95160m series 72 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m24) (fpt-64p-m24) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 2005 fujit s u limited f640 3 6 s -c-1-1 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95160m series 73 main changes (the main changes from the first edition to this edition) the vertical lines marked in the left side of the p age show the changes. page section change results ?? preliminary data sheet data sheet 22 i/o map changed as follows for r/w of reset factor register r r/w 29 electrical characteristics 1. absolute maximum ratings the min value in the row of ?operating temperature? is changed as follows; ? 40 ? 10 31 electrical characteristics 2. recommended operating conditions the min value in the row of ?operating temperature? is changed as follows; ? 40 ? 10 36 4. ac characteristics (1) clock timing added ?m ain pll multiplied by 4? in the clock frequency 38 (2) source clock/machine clock ? changed in the remarks of source clock cycle time (when using main clock) min : f ch = 16.25 mhz, pll multiplied by 1 min : f ch = 8.125 mhz, pll multiplied by 2 ? changed the footnote of *1; pll multiplication of main cl ock (select from 1, 2, 2.5 multiplication) pll multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) 39 ? added ? 4? in the main pll of ? ? outline of clock generation block? 41 changed the figure of ? ? main pll operation frequency? 52 to 55 (8) i 2 c timing added the characteristics 63 to 68 example characteristics added the example characteristics
mb95160m series f0709 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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